Responsibility
1. Design Nand Flash SSD Controller, and interface of software & hardware;
2. Write module spec and test-bench to meet the design criteria;
3. Being responsible for bug positioning in software-hardware debugging for ASIC layout and timing closure;
4. Integration, logic design and etc.
Qualification
1. EE master degree or above, 3 years or above experience of FPFA/ASIC Design;
2. Solid RTL coding， experienced in unit test;
3. Known basic ASIC back-end well, being familiar with PT, SDC and UPF low power;
4. Good command of C, Tcl, makefile and etc.;
5. Strong sense of self-driven and team-working.
Job Description
1. SoC design/integration/verification for SSD SoC projects;
2. IP evaluation/application/integration for 3rd-party IP, including CPU core, high-speed interfaces (DDR/PCIe), analog IP, etc.;
3. In-house IP design/verification, including RTL coding, linting, CDC checking, etc.;
4. SoC integration tasks, including synthesis, STA, formal checking, etc.;
Requirement
1. EE Master degree, 3 years of related working experience or above;
2. Familiar with RISC CPU and AMBA bus; NOC is plus;
3. Familiar with at least one interface of NAND flash, PCIe, DDR;
4. Familiar with usual peripherals, such as DMA, I2C, SPI, UART, JATG, etc.;
5. Familiar with RTL coding (Verilog or VHDL); C programming is plus;
6. Familiar with script languages, such as Perl, Python, Tcl, etc.;
7. Familiar with RTL cell-based design flow and related EDA tools;
8. Good at synthesis, STA, formal checking; DFT is plus;
9. Understand low-power design skills;
10. Good at reading and writing in English;
11. Good at documentation;
12. Good at communication, team work and strong sense of responsibility.
Responsibility
1. SoC DFT plan and pattern generation;
2. Automatic DFT flow building;
3. SoC DFT implementation, including scan insertion, ATPG test vector generation; boundary scan, functional test vectors, etc.;
4. Cowork with IP designers for high test coverage, such as PCIe, DDR,ONFI and etc.;
5. STA, power analysis and postsim for SoC DFT design.
Qualification
1. EE or Computer Master +5 years of working experience or above
2. Familiar with DFT flow; Mentor DFT flow is plus
3. Good at RTL coding and postsim
4. Good at synthesis, STA and formal checking
5. Good at ATE debugging, higher test coverage improvement
6. Familiar with script languages, such as Perl, Python, Tcl, etc.
7. Good at communication, team work and strong sense of responsibility
Responsibility
1. Work out high coverage rate chip/module verification plan;
2. Use System Verilog/UVM on module or chip verification;
3. Use simulation, FPGA and Emulator do performance analysis and verification;
4. Gate level simulation with SDF;
5. Provide test vector for ATE engineer;
6. SOC firmware test(C code);
7. Help FPGA engineer build and debug chip/module FPGA verification environment.
Qualification
1. EE, CS bachelor or above, 3Y+ IC design/verification experience;
2. Familiar with IC design flow;
3. Familiar with Cadence, Synopsys, Mentor logic simulation tools;
4. Familiar with Verilog and System Verilog;
5. Good understanding about coverage model, random constraint and verification methodology such as UVM/VMM/OVM and etc;
6. Good programming skills based on C/C++ esp. in embedded system;
7. PCIe, NVMe, DDR and Flash technology knowledge is preferred.
Responsibility
1. Design and optimize SSD products based on nand flash or next-generation memory devices for enterprise customers' requirements of low power consumption/reliability/cost/performance and other related indicators;
2. Collaborate with other firmware, systems and chip hardware engineers to define and design the SSD control chip architecture;
3. Assist in optimizing the firmware stack of next-generation SSD control chips;
4. Responsible for the design and optimization of SSD's core algorithm, and guaranteed the market competitiveness of the product through the analysis, evaluation, design and optimization of the algorithm;
5. Design other SSD products for mobile terminals and enterprise-level commercial applications in collaboration with chip architects;
6. Evaluate the quality and performance of the storage medium;
7. Pay close attention to and study the dynamics and cutting-edge technologies of the storage industry, especially ssd-related technologies, master the orientation and development trend of new technologies, evaluate and apply new technologies to SSD products.
Qualification
1. BS or above in CS or related, 8 years of firmware design; experience in storage industry; including 2 years of firmware architecture in SSD,HDD, storage system or related;
2. Deep understanding of enterprise SSD storage requirements and architecture;
3. Proficient in C language, familiar with CPU architectures such as ARM, and in-depth understanding of multi-threading and RTOS theory;
4. Have a deep understanding of the following storage interface protocols: PCIe/NVMe, AHCI, SATA, SAS, UFS, eMMC;
5. Experienced in advanced Nand flash and other non-volatile storage media, familiar with 3D Nand flash features;
6. Have a deep understanding of relevant software and firmware design methodology;
7. Have experience in firmware design and software development project management;
8. Master the latest firmware design and development tools and combine them with practical commercial application;
9. Good at coordination and team work under pressure.
Responsibility
1. Developed firmware required for enterprise-level storage systems;
2. Test and debug with systematic methods and professional skills;
3. Developed the whole storage system in close cooperation with SoC design and validation team, FPGA prototype design team and hardware design team;
4. Analyze product and system requirements to generate firmware module design;
5. Use various storage test instruments, analyzer and other debugging tools;
6. Write and review various engineering documents.
Qualification
1. Bachelor degree or above in electronic engineering or computer science, with at least 3 years of experience in firmware design and development;
2. Proficient in C language programming and debugging;
3. Knowledge and code optimization experience of programming development of ARM Cortex-R series or ARM Cortex-A series;
4. Knowledge and programming experience of PCIe protocol;
5. Familiar with various storage protocols such as SCSI, SAS and SATA;
6. Experience in NVM express protocol and driver development is preferred;
7. Experience in embedded Linux development is preferred;
8. NAND Flash knowledge and programming experience is preferred;
9. Good at communication and team work.
Responsibility
1. According to product design criteria，writing test cases and automated test scripts；
2. Develop test tool to ensure high test coverage；
3. Assist developer to position and analyze firmware bug；
4. Implement related test, documentation and track bug.
Qualification
1. EE or related, bachelor degree or above, 3 years of related experience or above;
2. Being familiar with C or Python;
3. Being familiar with Linux system;
4. Experienced in following items are preferred:
1) white-box test;
2) Storage System/HDD/SSD/Flash media/Disc driver/SATA、SAS、NVMe and etc.;
3) Embedded software development and test;
4) SPDK.
5. Good at team work and multi-jobs.
Responsibility
1. Develop storage, network related drivers under Linux/Windows
2. Develop and research storage related application software
3. Develop software kit for the company products
4. Help customer optimize the company products on their application software
5. Communicate with customer regularly for product feedback and new requirement
6. Develop and research cutting-edge storage technology.
Qualification
1. Master +3 years, or Bachelor +6 years working experience.
2. Good at C/C++ program/debug under Linux/Windows
3. Linux kernel and driver development experience are required
4. Familiar with embedded software development, understand embedded hardware architecture.
5. Windows driver development experience is preferred.
6. Storage/network driver and storage application software development experience are preferred.
7. Strong responsibility, good team work.
Responsibility
1. block/chip level physical design from netlist to GDSII flow
2. power planning , analysis and signoff check
3. physical verification (DRC/LVS/ANT/ERC)
Qualification
1. EE or related, bachelor degree or above, 3 years of project experience in physical PR design implementation or above;
2. Hand-on experience in DC/ICC2/Innovus/PT is preferred;
3. Good programming skill (Perl/TCL/Python) is a plus;
4. Successful tape-out experience is a strong plus;
5. Familiar with Linux Environment;
6. Good Listening, writing and speaking in English;
7. Good at communication and team work.
岗位职责
1. 负责全芯片级的DFT策略和方法学；
2. 建立DFT自动化流程,并且负责优化和维护；
3. 负责全芯片的DFT实现,包括SCAN插入,ATPG测试向量生成,边界扫描,功能性测试向量生成等；
4. 与前端工程师合作,负责IP的测试方案,比如PLL,PCIe,DDR,ONFI等；
5. 负责DFT相关设计实现(时序/功耗分析)，与前后端协作驱动芯片的设计实现顺利完成；
6. 参与DFT设计的RTL/门级仿真；
7. 部分参与SoC设计工作,包括数字电路设计,模块及全芯片级仿真和集成；
8. 部分参与设计实现工作,包括RTL综合,时序/功耗分析等。
任职要求
1. 电子类和通信类等相关专业，本科及以上学历，5年以上DFT和SoC设计经验,熟悉Mentor DFT flow 优先；
2. 能够熟练编写RTL代码并进行仿真,熟悉SoC设计；
3. 在ATE调试, 提高测试覆盖率以及减少DPPM方面均具备丰富的经验；
4. 熟悉综合和静态时序分析,熟悉形式验证；
5. 熟练掌握Verilog语言及Tcl,Perl,Shell,Python等脚本语言，掌握C语言；
6. 能够高效的解决问题，自我管理能力强，有团队合作精神。
Immediate delivery
